| 아래 코딩은 주파수가 IMHz 인데요 100Hz로 어떻게 바꿔줘야 되나요??
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port(
clk :in std_logic;
clear :in std_logic;
g :out std_logic_vector (7 downto 0);
seg7 :out std_logic_vector (7 downto 0));
end counter;
architecture arc of counter is
signal cnt :integer range 0 to 5;
signal num :integer range 0 to 15;
signal hour :integer range 0 to 59;
signal min, sec :integer range 0 to 59;
signal h10, h1 :integer range 0 to 9;
signal m10, m1 :integer range 0 to 9;
signal s10, s1 :integer range 0 to 9;
signal cnts :integer range 0 to 499999;
signal s_clk :std_logic;
signal m_clk :std_logic;
signal h_clk :std_logic;
component sep
port(
a : in integer range 0 to 63;
ten, one: out integer range 0 to 15);
end component;
component dec7
port(
bod : in integer range 0 to 15;
d : in std_logic;
seg : out std_logic_vector (7 downto 0));
end component;
begin
s_s : sep
port map (sec, s10, s1);
s_m : sep
port map (min, m10, m1);
s_h : sep
port map (hour, h10, h1);
s7 : dec7
port map (num, s_clk, seg7);
process (clk, clear)
begin
if (clear = 1) then
cnts <= 0;
s_clk <= ;
elsif (clk = 1 and clkevent) then
if (cnts >=499999) then
cnts <= 0;
s_clk <= not s_clk;
else
cnts <= cnts + 1;
end if;
end if;
end process;
process (s_clk, clear)
begin
if (clear = 1) then
sec <= 0;
elsif (s_clk = 1 and s_clkevent) then
if (sec >= 59) then
m_clk <= 1;
sec <= 0;
else
sec <= sec + 1;
m_clk <= ;
end if;
end if;
end process;
process (m_clk, clear)
begin
if (clear = 1) then
min <= 0;
elsif (m_clk = 1 and m_clkevent) then
if (min >= 59) then
h_clk <= 1;
min <= 0;
else
min <= min + 1;
h_clk <= ;
end if;
end if;
end process;
process (h_clk, clear)
begin
if (clear = 1) then
hour <= 0;
elsif (h_clk = 1 and h_clkevent) then
if (hour >= 23) then
hour <= 0;
else
hour <= hour + 1;
end if;
end if;
end process;
process (clk)
begin
if (clk = 1 and clkevent) then
case cnt is
when 0 =>
g <= 1111111;
num <= h10;
when 1 =>
g <= 10111111;
num <= h1;
when 2 =>
g <= 11011111;
num <= m10;
when 3 =>
g <= 11101111;
num <= m1;
when 4 =>
g <= 11110111;
num <= s10;
when 5 =>
g <= 11111011;
num <= s1;
when others =>
cnt <= 0;
end case;
cnt <= cnt + 1;
end if;
end process;
end arc;
--sep. vhd
entity sep is
port(
a : in integer range 0 to 59;
ten, one : out integer range 0 to 9);
end sep;
architecture a of sep is
begin
process(a)
begin
if a <= 9 then
ten <= 0;
one <= a;
elsif a <= 19 then
ten <= 1;
one <= a - 10;
elsif a <= 29 then
ten <= 2;
one <= a - 20;
elsif a <= 39 then
ten <= 3;
one <= a - 30;
elsif a <= 49 then
ten <= 4;
one <= a - 40;
elsif a <= 59 then
ten <= 5;
one <= a - 50;
else
ten <= 0;
one <= 0;
end if;
end process;
end a;
--dec7.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dec7 is
port(
bod : in integer range 0 to 15;
d : in std_logic;
seg : out std_logic_vector (7 downto 0));
end dec7;
architecture arc of dec7 is
signal y : std_logic_vector(6 downto 0);
begin
process (bod)
begin
case bod is
when 0 =>
y <= 1111110;
when 1 =>
y <= 110000;
when 2 =>
y <= 1101101;
when 3 =>
y <= 1111001;
when 4 =>
y <= 110011;
when 5 =>
y <= 1011011;
when 6 =>
y <= 1011111;
when 7 =>
y <= 1110000;
when 8 =>
y <= 1111111;
when 9 =>
y <= 1110011;
when 10 =>
y <= 1110111;
when 11 =>
y <= 011111;
when 12 =>
y <= 1001110;
when 13 =>
y <= 111101;
when 14 =>
y <= 1001111;
when 15 =>
y <= 1000111;
when others =>
y <= 000000;
end case;
end process;
seg <= y & d;
end arc;
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