| 우선은 너무 많은걸 물어봐서 바쁘실텐데 정말 죄송합니다.
제 사정이 워낙에 급해서요.. 시간이 수요일까지밖에 없거든요...
아래데로 코딩을 했는데 타겟보드에 돌려보니 한번 딱뜨고는 사라지더라구요..
유지는 안되는건가요??
제가 올린 모든글에 타겟보드와 디바이스는 처음것과 같습니다.
library ieee;
use ieee.std_logic_1164.all;
entity LCD_DISPLAY is
port (
clk : in std_logic;
e,rs_out,rw : out std_logic;
data : out std_logic_vector(7 downto 0));
end LCD_DISPLAY;
architecture arc of LCD_DISPLAY is
type LCD2 is (SYSTEM_SET, CLEAR_DISPLAY, ENTRY_MODE_SET, DISPLAY_ONOFF, WRITE);
signal LCD_MODE : LCD2;
type LCD1 is (LCD_SET,LINE1,LINE2,LINE3,LINE4,DELAY,CLEAR);
signal LCD_STATE : LCD1;
signal count_s : integer range 0 to 20;
signal delay_c : integer range 0 to 2;
signal dsp_data : std_logic_vector(7 downto 0);
signal rs : std_logic;
CONSTANT LCD_BLANK : std_logic_vector(7 downto 0) := 0100000;
CONSTANT LCD_DASH : std_logic_vector(7 downto 0) := 0101101;
CONSTANT LCD_COLON : std_logic_vector(7 downto 0) := 0111010;
CONSTANT LCD_period : std_logic_vector(7 downto 0) := 0101110;
CONSTANT LCD_0 : std_logic_vector(7 downto 0) := 0110000;
CONSTANT LCD_1 : std_logic_vector(7 downto 0) := 0110001;
CONSTANT LCD_2 : std_logic_vector(7 downto 0) := 0110010;
CONSTANT LCD_3 : std_logic_vector(7 downto 0) := 0110011;
CONSTANT LCD_4 : std_logic_vector(7 downto 0) := 0110100;
CONSTANT LCD_5 : std_logic_vector(7 downto 0) := 0110101;
CONSTANT LCD_6 : std_logic_vector(7 downto 0) := 0110110;
CONSTANT LCD_7 : std_logic_vector(7 downto 0) := 0110111;
CONSTANT LCD_8 : std_logic_vector(7 downto 0) := 0111000;
CONSTANT LCD_9 : std_logic_vector(7 downto 0) := 0111001;
CONSTANT LCD_A : std_logic_vector(7 downto 0) := 1000001;
CONSTANT LCD_B : std_logic_vector(7 downto 0) := 1000010;
CONSTANT LCD_C : std_logic_vector(7 downto 0) := 1000011;
CONSTANT LCD_D : std_logic_vector(7 downto 0) := 1000100;
CONSTANT LCD_E : std_logic_vector(7 downto 0) := 1000101;
CONSTANT LCD_F : std_logic_vector(7 downto 0) := 1000110;
CONSTANT LCD_G : std_logic_vector(7 downto 0) := 1000111;
CONSTANT LCD_H : std_logic_vector(7 downto 0) := 1001000;
CONSTANT LCD_I : std_logic_vector(7 downto 0) := 1001001;
CONSTANT LCD_J : std_logic_vector(7 downto 0) := 1001010;
CONSTANT LCD_K : std_logic_vector(7 downto 0) := 1001011;
CONSTANT LCD_L : std_logic_vector(7 downto 0) := 1001100;
CONSTANT LCD_M : std_logic_vector(7 downto 0) := 1001101;
CONSTANT LCD_N : std_logic_vector(7 downto 0) := 1001110;
CONSTANT LCD_O : std_logic_vector(7 downto 0) := 1001111;
CONSTANT LCD_P : std_logic_vector(7 downto 0) := 1010000;
CONSTANT LCD_Q : std_logic_vector(7 downto 0) := 1010001;
CONSTANT LCD_R : std_logic_vector(7 downto 0) := 1010010;
CONSTANT LCD_S : std_logic_vector(7 downto 0) := 1010011;
CONSTANT LCD_T : std_logic_vector(7 downto 0) := 1010100;
CONSTANT LCD_U : std_logic_vector(7 downto 0) := 1010101;
CONSTANT LCD_V : std_logic_vector(7 downto 0) := 1010110;
CONSTANT LCD_W : std_logic_vector(7 downto 0) := 1010111;
CONSTANT LCD_X : std_logic_vector(7 downto 0) := 1011000;
CONSTANT LCD_Y : std_logic_vector(7 downto 0) := 1011001;
CONSTANT LCD_Z : std_logic_vector(7 downto 0) := 1011010;
CONSTANT LCD_LCD_UNDER : std_logic_vector(7 downto 0) := 1011111;
CONSTANT LCD_S_a : std_logic_vector(7 downto 0) := 1100001;
CONSTANT LCD_S_b : std_logic_vector(7 downto 0) := 1100010;
CONSTANT LCD_S_c : std_logic_vector(7 downto 0) := 1100011;
CONSTANT LCD_S_d : std_logic_vector(7 downto 0) := 1100100;
CONSTANT LCD_S_e : std_logic_vector(7 downto 0) := 1100101;
CONSTANT LCD_S_f : std_logic_vector(7 downto 0) := 1100110;
CONSTANT LCD_S_g : std_logic_vector(7 downto 0) := 1100111;
CONSTANT LCD_S_h : std_logic_vector(7 downto 0) := 1101000;
CONSTANT LCD_S_i : std_logic_vector(7 downto 0) := 1101001;
CONSTANT LCD_S_j : std_logic_vector(7 downto 0) := 1101010;
CONSTANT LCD_S_k : std_logic_vector(7 downto 0) := 1101011;
CONSTANT LCD_S_l : std_logic_vector(7 downto 0) := 1101100;
CONSTANT LCD_S_m : std_logic_vector(7 downto 0) := 1101101;
CONSTANT LCD_S_n : std_logic_vector(7 downto 0) := 1101110;
CONSTANT LCD_S_o : std_logic_vector(7 downto 0) := 1101111;
CONSTANT LCD_S_p : std_logic_vector(7 downto 0) := 1110000;
CONSTANT LCD_S_q : std_logic_vector(7 downto 0) := 1110001;
CONSTANT LCD_S_r : std_logic_vector(7 downto 0) := 1110010;
CONSTANT LCD_S_s : std_logic_vector(7 downto 0) := 1110011;
CONSTANT LCD_S_t : std_logic_vector(7 downto 0) := 1110100;
CONSTANT LCD_S_u : std_logic_vector(7 downto 0) := 1110101;
CONSTANT LCD_S_v : std_logic_vector(7 downto 0) := 1110110;
CONSTANT LCD_S_w : std_logic_vector(7 downto 0) := 1110111;
CONSTANT LCD_S_x : std_logic_vector(7 downto 0) := 1111000;
CONSTANT LCD_S_y : std_logic_vector(7 downto 0) := 1111001;
CONSTANT LCD_S_z : std_logic_vector(7 downto 0) := 1111010;
CONSTANT add_line_1 : std_logic_vector(7 downto 0) := 10000000;
CONSTANT add_line_2 : std_logic_vector(7 downto 0) := 11000000;
CONSTANT add_line_3 : std_logic_vector(7 downto 0) := 10010100;
CONSTANT add_line_4 : std_logic_vector(7 downto 0) := 11010100;
begin
process(clk)
variable count : integer range 0 to 21;
variable cnt_d : integer range 0 to 20;
begin
if clk = 1 and clkevent then
count := count +1;
case LCD_STATE is
when LCD_SET =>
if count = 14 then
count := 0;
LCD_STATE <= LINE1;
end if;
when LINE1 =>
if count = 21 then -- last address count := 0;
LCD_STATE <= LINE2;
end if;
when LINE2 =>
if count = 21 then -- last address count := 0;
LCD_STATE <= LINE3;
end if;
when LINE3 =>
if count = 21 then -- last address count := 0;
LCD_STATE <= LINE4;
end if;
when LINE4 =>
if count = 21 then -- last address count := 0;
LCD_STATE <= DELAY;
end if;
when DELAY =>
if count = 20 then
cnt_d := cnt_d + 1; count := 0;
end if;
if count = 15 then
cnt_d := 16;
LCD_STATE <= CLEAR;
elsif cnt_d = 20 then
cnt_d := 0;
LCD_STATE <= LINE1;
else
LCD_STATE <= DELAY;
end if;
when CLEAR =>
count := 0;
LCD_STATE <= DELAY;
end case;
count_s <= count;
end if;
end process;
process (clk)
variable cnt_v : integer range 0 to 20;
begin
cnt_v := count_s;
case LCD_STATE is
when LCD_SET =>
rs <= ;
--LINE1
when LINE1 =>
CASE cnt_v IS
WHEN 0 =>
rs <= ;
dsp_data <= add_line_1;
WHEN 1 =>
rs <= 1;
dsp_data <= LCD_W; --W
WHEN 2 =>
rs <= 1;
dsp_data <= LCD_S_e; --e
WHEN 3 =>
rs <= 1;
dsp_data <= LCD_S_l; --l
WHEN 4 =>
rs <= 1;
dsp_data <= LCD_S_c; --c
WHEN 5 =>
rs <= 1;
dsp_data <= LCD_S_o; --o
WHEN 6 =>
rs <= 1;
dsp_data <= LCD_S_m; --m
WHEN 7 =>
rs <= 1;
dsp_data <= LCD_S_e; --e
WHEN 8 =>
rs <= 1;
dsp_data <= 0100001; --!
WHEN 9 =>
rs <= 1;
dsp_data <= LCD_BLANK; --
WHEN 10 =>
rs <= 1;
dsp_data <= LCD_V; --Y
WHEN 11 =>
rs <= 1;
dsp_data <= LCD_H; --H
WHEN 12 =>
rs <= 1;
dsp_data <= LCD_D; --D
WHEN 13 =>
rs <= 1;
dsp_data <= LCD_L; --L
WHEN 14 =>
rs <= 1;
dsp_data <= LCD_BLANK; --
WHEN 15 =>
rs <= 1;
dsp_data <= LCD_D; --D
WHEN 16 =>
rs <= 1;
dsp_data <= LCD_S_e; --e
WHEN 17 =>
rs <= 1;
dsp_data <= LCD_S_s; --s
WHEN 18 =>
rs <= 1;
dsp_data <= LCD_S_i; --i
WHEN 19 =>
rs <= 1;
dsp_data <= LCD_S_g; --g
WHEN 20 =>
rs <= 1;
dsp_data <= LCD_S_n; --
END CASE;
--LINE2
when LINE2 =>
CASE cnt_v IS
WHEN 0 =>
rs <= ;
dsp_data <= add_line_2;
WHEN 1 =>
rs <= 1;
dsp_data <= LCD_BLANK; --
WHEN 2 =>
rs <= 1;
dsp_data <= 0111100; --<
WHEN 3 =>
rs <= 1;
dsp_data <= LCD_BLANK; --
WHEN 4 =>
rs <= 1;
dsp_data <= LCD_D; --D
WHEN 5 =>
rs <= 1;
dsp_data <= LCD_S_i; --i
WHEN 6 =>
rs <= 1;
dsp_data <= LCD_S_s; --s
WHEN 7 =>
rs <= 1;
dsp_data <= LCD_S_p; --p
WHEN 8 =>
rs <= 1;
dsp_data <= LCD_S_l; --l
WHEN 9 =>
rs <= 1;
dsp_data <= LCD_S_a; --a
WHEN 10 =>
rs <= 1;
dsp_data <= LCD_S_y; --y
WHEN 11 =>
rs <= 1;
dsp_data <= LCD_BLANK; --
WHEN 12 =>
rs <= 1;
dsp_data <= LCD_T; --T
WHEN 13 =>
rs <= 1;
dsp_data <= LCD_S_o; --o
WHEN 14 =>
rs <= 1;
dsp_data <= LCD_B |
