| --lcd_dp1.vhd
이중에서 어떤걸 바꿔야 하는지???????주석으로..!!
생사가 달린 문제입니다^^;;;;
d(10khz)로 맞추면 문자가 순식간에 지나가는 구조로 되고 100khz로 되면 시계가 안가거든요!!!!
library ieee;
use ieee.std_logic_1164.all;
entity lcd_dp1 is
port(
clk:in std_logic;
clr:in std_logic;
e,rs_out,rw:out std_logic;
data:out std_logic_vector(7 downto 0));
end lcd_dp1;
architecture arc of lcd_dp1 is
type lcd_set is (system_set,clear_display,entry_mode_set,display_onoff,write);
signal lcd_mode:lcd_set;
type lcd1 is (lcd_set,line1,line2,line3,line4,delay,clear);
signal lcd_state:lcd1;
signal count_s:integer range 0 to 20;
signal delay_c:integer range 0 to 2;
signal cnt:integer range 0 to 49;
signal chk:std_logic;
signal dsp_data:std_logic_vector(7 downto 0);
signal rs:std_logic;
signal lcds1,lcds2:std_logic_vector(7 downto 0);
signal lcdm1,lcdm2:std_logic_vector(7 downto 0);
signal lcdh1,lcdh2:std_logic_vector(7 downto 0);
component clock
port(
clk:in std_logic;
clear:in std_logic;
lcds1:out std_logic_vector(7 downto 0);
lcds2:out std_logic_vector(7 downto 0);
lcdm1:out std_logic_vector(7 downto 0);
lcdm2:out std_logic_vector(7 downto 0);
lcdh1:out std_logic_vector(7 downto 0);
lcdh2:out std_logic_vector(7 downto 0));
end component;
constant l_blank:std_logic_vector(7 downto 0):= 0100000;
constant l_sc:std_logic_vector(7 downto 0):= 0111010;
constant l_box:std_logic_vector(7 downto 0):=11111111;
begin
c_k:clock
port map(clk,clr,lcds1,lcds2,lcdm1,lcdm2,lcdh1,lcdh2);
process(clk)
variable count:integer range 0 to 21;
variable cnt_d:integer range 0 to 20;
begin
if clk=1 and clkevent then
count:= count+1;
case lcd_state is
when lcd_set=>
if count=14 then
count:=0;
lcd_state<=line1;
end if;
when line1=>
if count=21 then
lcd_state<=line2;
end if;
when line2=>
if count=21 then
lcd_state<=line3;
end if;
when line3=>
if count=21 then
lcd_state<=line4;
end if;
when line4=>
if count=21 then
lcd_state<=delay;
end if;
when delay=>
if count=20 then
cnt_d:=cnt_d+1;
count:=0;
end if;
if cnt_d=15 then
cnt_d:=16;
lcd_state<=clear;
elsif cnt_d=20 then
cnt_d:=0;
lcd_state<=line1;
else
lcd_state<=delay;
end if;
when clear=>
count:=0;
lcd_state<=delay;
end case;
count_s<=count;
end if;
end process;
process(clk)
variable cnt_v:integer range 0 to 20;
begin
cnt_v:=count_s;
case lcd_state is
when lcd_set=>
rs<= ;
when line1=>
case cnt_v is
when 0=>
rs<=1;
dsp_data<= 0110010;
when 1=>
rs<=1;
dsp_data<= 0110000;
when 2=>
rs<=1;
dsp_data<= 0110000;
when 3=>
rs<=1;
dsp_data<= 0110010;
when 4=>
rs<=1;
dsp_data<= 0110001;
when 5=>
rs<=1;
dsp_data<= 0110110;
when 6=>
rs<=1;
dsp_data<= 0110000;
when 7=>
rs<=1;
dsp_data<= 0110011;
when 8=>
rs<=1;
dsp_data<= 0110111;
when 9=>
rs<=1;
dsp_data<= 0100110;
when 10=>
rs<=1;
dsp_data<= 0110010;
when 11=>
rs<=1;
dsp_data<= 0110000;
when 12=>
rs<=1;
dsp_data<= 0110000;
when 13=>
rs<=1;
dsp_data<= 0110010;
when 14=>
rs<=1;
dsp_data<= 0110001;
when 15=>
rs<=1;
dsp_data<= 0110110;
when 16=>
rs<=1;
dsp_data<= 0110001;
when 17=>
rs<=1;
dsp_data<= 0110101;
when 18=>
rs<=1;
dsp_data<= 0110011;
when others=>
rs<=1;
dsp_data<=l_box;
end case;
when line2=>
case cnt_v is
when 0=>
rs<= ;
dsp_data<=11000000;
when others=>
rs<=1;
dsp_data<=l_box;
end case;
when line3=>
case cnt_v is
when 0=>
rs<= ;
dsp_data<=10010100;
when 1=>
rs<=1;
dsp_data<=l_box;
when 2=>
rs<=1;
dsp_data<=l_box;
when 3=>
rs<=1;
dsp_data<=l_blank;
when 4=>
rs<=1;
dsp_data<=l_blank;
when 5=>
rs<=1;
dsp_data<=lcdh2;
when 6=>
rs<=1;
dsp_data<=lcdh1;
when 7=>
rs<=1;
dsp_data<=l_blank;
when 8=>
rs<=1;
dsp_data<=l_sc;
when 9=>
rs<=1;
dsp_data<=l_blank;
when 10=>
rs<=1;
dsp_data<=lcdm2;
when 11=>
rs<=1;
dsp_data<=lcdm1;
when 12=>
rs<=1;
dsp_data<=l_blank;
when 13=>
rs<=1;
dsp_data<=l_sc;
when 14=>
rs<=1;
dsp_data<=l_blank;
when 15=>
rs<=1;
dsp_data<=lcds2;
when 16=>
rs<=1;
dsp_data<=lcds1;
when 17=>
rs<=1;
dsp_data<=l_blank;
when 18=>
rs<=1;
dsp_data<=l_blank;
when 19=>
rs<=1;
dsp_data<=l_box;
when 20=>
rs<=1;
dsp_data<=l_box;
end case;
when line4=>
case cnt_v is
when 0=>
rs<= ;
dsp_data<=11010100;
when others=>
rs<=1;
dsp_data<=l_box;
end case;
when delay=>
rs<= ;
dsp_data<= 0000010;
when clear=>
rs<= ;
dsp_data<= 0000001;
end case;
end process;
process(clk)
begin
if clk=1 and clkevent then
if cnt>49 then
chk<=not chk;
cnt<=0;
else
cnt<=cnt+1;
end if;
end if;
end process;
process(chk)
begin
if chk=1 and chkevent then
delay_c<=delay_c+1;
if delay_c=1 then
case lcd_mode is
when system_set=>
lcd_mode<=clear_display;
when clear_display=>
lcd_mode<=entry_mode_set;
when entry_mode_set=>
lcd_mode<=display_onoff;
when display_onoff=>
lcd_mode<=write;
when others=>
lcd_mode<=write;
end case;
elsif delay_c=2 then
delay_c<=0;
end if;
end if;
end process;
process(lcd_mode,clk)
begin
case lcd_mode is
when system_set=>
rs_out<= ;
rw<= ;
data<= 0111100;
when clear_display=>
rs_out<= ;
rw<= ;
data<= 0000001;
when entry_mode_set=>
rs_out<= ;
rw<= ;
data<= 0000110;
when display_onoff=>
rs_out<= ;
rw<= ;
data<= 0001110;
when write=>
rs_out<=rs;
rw<= ;
data<=dsp_data;
end case;
e<=clk;
end process;
end arc;
--sep.vhd
entity sep is
port(
a: in integer range 0 to 63;
ten,one:out integer range 0 to 15);
end sep;
architecture a of sep is
begin
process(a)
begin
if a<=9 then
ten<=0;
one<=a;
elsif a<=19 then
ten<=1;
one<=a-10;
elsif a<=29 then
ten<=2;
one<=a-20;
elsif a<=39 then
ten<=3;
one<=a-30;
elsif a<=49 then
ten<=4;
one<=a-40;
elsif a<=59 then
ten<=5;
one<=a-50;
else
ten<=0;
one<=0;
end if;
end process;
end a;
--clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity clock is
port (
clk :in std_logic;
clear :in std_logic;
lcds1 :out std_logic_vector(7 downto 0);
lcds2 :out std_logic_vector(7 downto 0);
lcdm1 :out std_logic_vector(7 downto 0);
lcdm2 :out std_logic_vector(7 downto 0);
lcdh1 :out std_logic_vector(7 downto 0);
lcdh2 :out std_logic_vector(7 downto 0));
end clock;
architecture arc of clock is
signal s,m,h :std_logic;
signal cnt :integer range 0 to 4999;
signal s_cnt,m_cnt,h_cnt :integer range 0 to 63;
signal s1,s2,m1,m2,h1,h2 :integer range 0 to 15;
component sep
port(
a :in integer range 0 to 63;
ten,one :out integer range 0 to 15);
end component;
component dp
port(
bcd :in integer range 0 to 15;
lcd :out std_logic_vector(7 downto 0));
end component;
begin
s_s:sep
port map(s_cnt,s2,s1);
s_m:sep
port map(m_cnt,m2,m1);
s_h:sep
port map(h_cnt,h2,h1);
sec1:dp
port map(s1,lcds1);
sec2:dp
port map(s2,lcds2);
min1:dp
port map(m1,lcdm1);
min2:dp
port map(m2,lcdm2);
hour1:dp
port map(h1,lcdh1);
hour2:dp
port map(h2,lcdh2);
process(clk,clear)
begin
--generate second
if clear=1 then
cnt<=0;
s<= ;
elsif (clk=1 and clkevent) then
if (cnt>=4999) then
cnt<=0;
s<=not s;
else
cnt<=cnt+1;
end if;
end if;
end process;
--generate minute
process(clear,s)
begin
if clear=1 then
s_cnt<=0;
m<= ;
elsif (s=1 and sevent) then
if s_cnt>=59 then
s_cnt<=0;
m<=1;
else
s_cnt<=s_cnt+1;
m<= ;
end if;
end if;
end process;
process(clear,m)
begin
if clear=1 then
m_cnt<=0;
h<= ;
elsif (m=1 and mevent) then
if m_cnt>=59 then
m_cnt<=0;
h<=1;
else
m_cnt<=m_cnt+1;
h<= ;
end if;
end if;
end process;
process(clear,h) --limit 24 hour
begin
if clear=1 then
h_cnt<=0;
elsif (h=1 and hevent) then
if h_cnt>=23 then
h_cnt<=0;
else
h_cnt<=h_cnt+1;
end if;
end if;
end process;
end arc;
--dp.vhd
library ieee;
use ieee.std_logic_1164.all;
entity dp is
port(
bcd:in integer range 0 to 15;
lcd:out std_logic_vector(7 downto 0));
end dp;
architecture arc of dp is
begin
process(bcd)
begin
case bcd is
when 0=>
lcd<= 0110000;
when 1=>
lcd<= 0110001;
when 2=>
lcd<= 0110010;
when 3=>
lcd<= 0110011;
when 4=>
lcd<= 0110100;
when 5=>
lcd<= 0110101;
when 6=>
lcd<= 0110110;
when 7=>
lcd<= 0110111;
when 8=>
lcd<= 0111000;
when 9=>
lcd<= 0111001;
when others=>
lcd<= 0100000;
end case;
end process;
end arc;
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